1. Field of the Invention
The present invention relates in general to a gate array, LSI and more specifically to a semiconductor memory capable of non-destructive read-out operation, employing the geometrical configuration of the gate array LSI.
2. Description of the Prior Art
Various layout designs for a semiconductor integrated circuit may be prepared according to a scale of the integrated circuit and design approach. A fully-custom IC in which all layers are designed and manufactured for exclusive use is suited for the case where a large number of high performance ICs are to be manufactured. In contrast, a semicustom IC such as the gate array LSI or the Application-Specific Integrated Circuits (ASICs) in which layers located below a wiring layer level are manufactured in advance and then only wiring layers are designed and manufactured is suited for the case where specific-application ICs are to be manufactured in a short term. In addition, the semicustom IC has such an advantage that design cost and production cost can be reduced. However, as a semiconductor memory employing the geometrical configuration of the gate array LSI, only an SRAM (Static Random Access Memory) in which each cell being constructed of six transistors is known until now. This is because such six-transistor SRAMs can be made of only CMOS transistors arranged in the gate array configuration, having an excellent stability of the circuit.
With reference to FIGS. 1, 2A, and 2B, the following will describe a circuit construction of the six-transistor SRAMs based on the conventional gate array configuration. FIG.1 shows a pattern of the basic cell which basically makes up each memory cell in a gate array. This basic cell comprises an nMOS region 11 and a pMOS region 13. In the nMOS region 11, two gate electrodes 16 are disposed in parallel. On the upper and the lower sides of a pair of these gate electrodes 16, an n.sup.+ diffused region 25 is formed respectively, while between these two electrodes 16, a common n.sup.+ diffused region 26 is formed, thus constructing two nMOS transistors. The n.sup.+ diffused region 25 and n.sup.+ diffused region 26 may be called an n.sup.+ source region and n.sup.+ drain region 26, respectively, in a case. In another case, these regions 25, 26 may be called as an n+ drain region 25 and n.sup.+ source region 26, respectively, depending on a circuit configuration employed. Similarly, in the pMOS region 13, two gate electrodes 15 are disposed in parallel. On the upper and the lower sides of these two gate electrodes 15, a p.sup.+ diffused region 21 is formed respectively, while between these two electrodes 15, a common p.sup.+ diffused region 22 is formed, thus constructing two pMOS transistors. The p.sup.+ diffused region 21 and the p.sup.+ diffused region 22 may be called a p.sup.+ source region 21 and p.sup.+ drain region 22 respectively and vice versa, depending on the circuit configuration. As known in the art, the nMOS transistor and pMOS transistor is formed in symmetry, which n.sup.+ diffused region or p.sup.+ diffused region is called as the source region is a mere matter of naming. That is, each basic cell in the gate array configuration can make up two nMOS transistors and another two pMOS transistors.
In order to use such a layout of basic cell to construct a six-transistor memory cell in an SRAM such as shown in FIG. 2A, it is necessary to use two basic cells 301 and 302 as shown in FIG. 2B. In FIG. 2B, between the basic cell 301 shown on the upper side and the basic cell 302 shown on the lower side, an n.sup.+ contact region 31 for an n-well and also a p.sup.+ contact region 32 for a p-well are disposed. These two basic cells 301 and 302 are used to form three nMOS transistors of N11, N12, and N13 as well as three pMOS transistors of P11, P12, and P13. On these two basic cells, an SRAM cell is constructed, and a plurality of SRAM cells, each of which is constructed of six transistors, has been disposed on an LSI chip to form an X-Y matrix. Note here that signal names WB, RB, WW, and RW stand for Write Bit, Read Bit, Write Word, and Read Word respectively.
The nMOS transistor N11 has its n.sup.+ source region 25 connected via a contact hole 66 to a WB wiring 55 at first metal level, while the nMOS transistors N12 and N13 have their respective n.sup.+ source regions connected through the contact hole 66 to a low-voltage power supply (VSS) wiring 52 at first metal level. Also, a gate electrode 16 of the nMOS transistor N11 is connected to a WW wiring 54 at second metal level through via hole 88, first metal level wiring and contact hole 66. The first metal level wiring is formed just under the via hole 88 and not shown in FIG. 2B. On the other hand, the pMOS transistor P11 has its p.sup.+ source region 21 connected to an RB wiring 51 at first metal level and also the pMOS transistors P12 and P13 have their respective p.sup.+ source regions 21 connected to a high-level power supply at first metal level (VDD) wiring 56 through the contact hole 66 respectively. Also, a gate electrode 15 of the pMOS transistor P11 is connected to an RW wiring 53 at second metal level through via hole 88, first metal level wiring and the contact hole 66. The first metal level wiring is formed just under the via hole 88 and not shown in FIG. 2B.
As shown in FIG. 2B, the conventional type of a semiconductor IC memory has been implemented with a six-transistor/memory-cell configuration of an SRAM type, so that two basic cells of 301 and 302 have been required to configure each memory cell with three nMOS transistors and another three pMOS transistors. Therefore, the integration density has been very hard to increase and the memory capacity also has been restricted as a matter of course. Moreover, this conventional type is rather hard to manufacture because it takes six transistors for each memory cell and therefore has a complicated wiring.
As described so far, in a conventional gate array LSI, a plurality of SRAM cells each of which is constructed of six transistors has been disposed. And only the SRAM cell is known, while DRAM type cell is not developed, because the layout of the basic cells in the gate array LSI is considered being not suited for DRAM cells. Especially, it was difficult to construct a storage capacitor having an enough capacitance for the DRAM cell by the gate array layout.